[
  {
    "EventName": "l2_request_g1.group2",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
    "UMask": "0x01"
  },
  {
    "EventName": "l2_request_g1.l2_hwpf",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests from hardware prefetchers to prefetch directly into L2 (hit or miss).",
    "UMask": "0x02"
  },
  {
    "EventName": "l2_request_g1.prefetch_l2_cmd",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests to prefetch directly into L2.",
    "UMask": "0x04"
  },
  {
    "EventName": "l2_request_g1.cacheable_ic_read",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for instruction cache reads.",
    "UMask": "0x10"
  },
  {
    "EventName": "l2_request_g1.ls_rd_blk_c_s",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for data cache shared reads.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_request_g1.rd_blk_x",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for data cache stores.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_request_g1.rd_blk_l",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for data cache reads (includes hardware and software prefetches).",
    "UMask": "0x80"
  },
  {
    "EventName": "l2_request_g1.dc_all",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of common types from data cache (includes prefetches).",
    "UMask": "0xe0"
  },
  {
    "EventName": "l2_request_g1.no_pf_all",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of common types not including prefetches.",
    "UMask": "0xf1"
  },
  {
    "EventName": "l2_request_g1.all",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of all types.",
    "UMask": "0xf7"
  },
  {
    "EventName": "l2_request_g2.ls_rd_sized_nc",
    "EventCode": "0x61",
    "BriefDescription": "L2 cache requests for non-coherent, non-cacheable LS sized reads.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_request_g2.ls_rd_sized",
    "EventCode": "0x61",
    "BriefDescription": "L2 cache requests for coherent, non-cacheable LS sized reads.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_request_g2.all",
    "EventCode": "0x61",
    "BriefDescription": "L2 cache requests of all rare types.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_wcb_req.wcb_close",
    "EventCode": "0x63",
    "BriefDescription": "Write Combining Buffer (WCB) closures.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_cache_req_stat.ic_fill_miss",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 misses.",
    "UMask": "0x01"
  },
  {
    "EventName": "l2_cache_req_stat.ic_fill_hit_s",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits on non-modifiable lines.",
    "UMask": "0x02"
  },
  {
    "EventName": "l2_cache_req_stat.ic_fill_hit_x",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits on modifiable lines.",
    "UMask": "0x04"
  },
  {
    "EventName": "l2_cache_req_stat.ic_hit_in_l2",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 hits.",
    "UMask": "0x06"
  },
  {
    "EventName": "l2_cache_req_stat.ic_access_in_l2",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the instruction cache that result in L2 accesses.",
    "UMask": "0x07"
  },
  {
    "EventName": "l2_cache_req_stat.ls_rd_blk_c",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 misses.",
    "UMask": "0x08"
  },
  {
    "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 misses.",
    "UMask": "0x09"
  },
  {
    "EventName": "l2_cache_req_stat.ls_rd_blk_x",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) that result in data cache stores or L2 state change hits.",
    "UMask": "0x10"
  },
  {
    "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits on non-modifiable lines.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits on modifiable lines.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 read hits on shared lines.",
    "UMask": "0x80"
  },
  {
    "EventName": "l2_cache_req_stat.dc_hit_in_l2",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 hits.",
    "UMask": "0xf0"
  },
  {
    "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 hits.",
    "UMask": "0xf6"
  },
  {
    "EventName": "l2_cache_req_stat.dc_access_in_l2",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache that result in L2 accesses.",
    "UMask": "0xf8"
  },
  {
    "EventName": "l2_cache_req_stat.all",
    "EventCode": "0x64",
    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) from the data cache and the instruction cache that result in L2 accesses.",
    "UMask": "0xff"
  },
  {
    "EventName": "l2_pf_hit_l2.l2_hwpf",
    "EventCode": "0x70",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers.",
    "UMask": "0x1f"
  },
  {
    "EventName": "l2_pf_hit_l2.l1_dc_hwpf",
    "EventCode": "0x70",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers.",
    "UMask": "0xe0"
  },
  {
    "EventName": "l2_pf_hit_l2.l1_dc_l2_hwpf",
    "EventCode": "0x70",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers.",
    "UMask": "0xff"
  },
  {
    "EventName": "l2_pf_miss_l2_hit_l3.l2_hwpf",
    "EventCode": "0x71",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers.",
    "UMask": "0x1f"
  },
  {
    "EventName": "l2_pf_miss_l2_hit_l3.l1_dc_hwpf",
    "EventCode": "0x71",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers.",
    "UMask": "0xe0"
  },
  {
    "EventName": "l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf",
    "EventCode": "0x71",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers.",
    "UMask": "0xff"
  },
  {
    "EventName": "l2_pf_miss_l2_l3.l2_hwpf",
    "EventCode": "0x72",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers.",
    "UMask": "0x1f"
  },
  {
    "EventName": "l2_pf_miss_l2_l3.l1_dc_hwpf",
    "EventCode": "0x72",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers.",
    "UMask": "0xe0"
  },
  {
    "EventName": "l2_pf_miss_l2_l3.l1_dc_l2_hwpf",
    "EventCode": "0x72",
    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers.",
    "UMask": "0xff"
  },
  {
    "EventName": "l2_fill_rsp_src.local_ccx",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from L3 cache or different L2 cache in the same CCX.",
    "UMask": "0x02"
  },
  {
    "EventName": "l2_fill_rsp_src.near_cache",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from cache of another CCX in the same NUMA node.",
    "UMask": "0x04"
  },
  {
    "EventName": "l2_fill_rsp_src.dram_io_near",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from either DRAM or MMIO in the same NUMA node.",
    "UMask": "0x08"
  },
  {
    "EventName": "l2_fill_rsp_src.far_cache",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from cache of another CCX in a different NUMA node.",
    "UMask": "0x10"
  },
  {
    "EventName": "l2_fill_rsp_src.dram_io_far",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from either DRAM or MMIO in a different NUMA node.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_fill_rsp_src.dram_io_all",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from either DRAM or MMIO in the same or a different NUMA node.",
    "UMask": "0x48"
  },
  {
    "EventName": "l2_fill_rsp_src.far_all",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from either cache of another CCX, DRAM or MMIO in a different NUMA node.",
    "UMask": "0x50"
  },
  {
    "EventName": "l2_fill_rsp_src.alt_mem",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from extension memory (CXL).",
    "UMask": "0x80"
  },
  {
    "EventName": "l2_fill_rsp_src.all",
    "EventCode": "0x165",
    "BriefDescription": "L2 cache fills where data is returned from all types of sources.",
    "UMask": "0xde"
  },
  {
    "EventName": "l2_sys_bw.local_dram_fill",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for fill events that target the same NUMA node and return from DRAM in the same NUMA node.",
    "UMask": "0x01"
  },
  {
    "EventName": "l2_sys_bw.remote_dram_fill",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for fill events that target a different NUMA node and return from DRAM in a different NUMA node.",
    "UMask": "0x02"
  },
  {
    "EventName": "l2_sys_bw.nt_write",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for non-temporal write events that target all NUMA nodes.",
    "UMask": "0x04"
  },
  {
    "EventName": "l2_sys_bw.local_scm_fill",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for fill events that target the same NUMA node and return from extension memory (CXL) in the same NUMA node.",
    "UMask": "0x10"
  },
  {
    "EventName": "l2_sys_bw.remote_scm_fill",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for fill events that target a different NUMA node and return from extension memory (CXL) in a different NUMA node.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_sys_bw.victim",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for cache victim events that target all NUMA nodes.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_sys_bw.all",
    "EventCode": "0x175",
    "BriefDescription": "System bandwidth utilization for all types of events (total utilization).",
    "UMask": "0xff"
  }
]