bin/busgen
bin/capgen
bin/cubegen
bin/fastcap
bin/pipedgen
bin/pyragen
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/1x1bus.lst
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/1x1coarse.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/1x1fine.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/1x1nonuni.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/README
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/big_sphere1.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coated_sph.lst
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/cond_air_1x1.qui
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/cond_dielec_1x1.qui
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/connector2.sh
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/connector3.sh
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/connector4.sh
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/cubeeg.fig
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dielec_face.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dielec_sides.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dielec_sides_2x2.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dielec_topbot.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/pin
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/pipeeg.fig
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell.lst
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell_bitl.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell_botd.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell_cond.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell_gnd.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell_test.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramcell_topd.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ramgen.sh
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sphere1.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sphere2.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sphere3.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testgen.sh
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testrun.sh
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/via.neu
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/Makefile
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/1x1bus.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/1x1coarse.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/1x1fine.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/1x1nonuni.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/big_sphere1.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/coated_sph.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/dielec_face.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/dielec_sides.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/dielec_sides_2x2.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/dielec_topbot.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell_bitl.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell_botd.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell_cond.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell_gnd.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell_test.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/ramcell_topd.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/sphere1.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/sphere2.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/sphere3.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/results/via.out
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/work/run
%%PORTDOCS%%%%DOCSDIR%%/readme.gz
%%PORTDOCS%%%%DOCSDIR%%/FastCapsuppl.pdf
%%PORTDOCS%%%%DOCSDIR%%/fastcap_paper.pdf
%%PORTDOCS%%%%DOCSDIR%%/ug.pdf